Host Interfacing at a Gigabit
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A major goal of the host interface architecture which has been developed at UPenn is to be sufficiently flexible as to allow implementation using a range of technologies. These technologies can provide the performance necessary for operation in the emerging high bandwidth ATM networking environments. This paper examines the feasibility of reimplementing the current instantiation of the architecture which operates at 160 Mbps to allow for operation in the 600+ Mbps domain.
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1993-04-21
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University of Pennsylvania Department of Computer and Information Science Technical Report No. MS-CIS-93-43.