Symbolic Simulator/Debugger for the Systolic/Cellular Array Processor

This document describes an implementation of a symbolic simulator/debugger for the Systolic/Cellular Array Processor (SCAP), which is currently being built at Hughes Research Laboratories. The SCAP system is a parallel computer with 256 identical processing elements (PEs) connected using a mesh interconnection network in a 16 x 16 grid. Each PE features a two-bus internal architecture, with seven functional units, and four I/O ports used to communicate with its four neighboring PEs. All functional units operate on 32-bit fixed point data. The reader is refered to [Przytula,88] for a detailed description of SCAP's architecture, data representation format, and machine level operation of the system.