Xu, ChaoLaker, Kenneth RSargeant, WinslowVan der Spiegel, Jan2023-05-222023-05-222003-07-012006-01-19https://repository.upenn.edu/handle/20.500.14332/33336A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.Electrical and Computer EngineeringArticle