Van der Spiegel, Jan

Disciplines

Electrical and Electronics

Position

Professor of Electrical Science and Engineering

Introduction

Research Interests Vision Sensors: We are studying novel current-mode image sensors with analog spatial processing and a new pixel array design, in which several techniques are combined to improve the quality of the images. Included in the design is a new addressing scheme that allows a group of pixels to share the same readout circuitry, therefore reducing the pixel size and increasing the resolution. The new design has removed the in-pixel accessing switches, and uses velocity saturated operation in order to increase the readout linearity. We are also integrating a successive approximation ADC on the imager. The ADC is natively current mode, and is designed to interface directly with the current mode pixels without the need for sample-and-hold circuits or current-to-voltage converters. Sensor for Polarization Imaging: We are also developing a focal plane imaging sensor capable of real time extraction of polarization information. The imaging system consists of a photo array of linear current mode active pixel sensors and analog processing circuitry for computation of the Stokes parameters. A dual-tier thin film micro-polarizer array has been deposited on the imager. A commercially available thin film polarizer is used to create an array of micro-polarizers. The thin film polarizer consists of an iodine-doped Polyvinyl Alcohol (PVA) layer which is patterned and etched using RIE. The measured extinction ratios of the filters are 1000 and 100 for the blue/green and red spectrum, respectively. Mixed mode Integrated Circuits for Data Acquisition Systems and Communications: We are currently exploring different architectures and algorithms to realize high performance analog-to-digital converters. One project deals background calibration schemes to correct for any residual non-idealities (linear and non-linear) in pipe-lined analog-to-digital converters. We are also developing CMOS circuits for RF communications using AlN Contour-Mode Piezoelectric Resonators in collaboration with Prof. G. Lucca’s group.

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Now showing 1 - 10 of 47

Linear Current-Mode Active Pixel Sensor
(2007-11-01) Philipp, Ralf M; Gruev, Viktor; Orr, David; Van der Spiegel, Jan; Etienne-Cummings, Ralph
A current mode CMOS active pixel sensor (APS) providing linear light-to-current conversion with inherently low fixed pattern noise (FPN) is presented. The pixel features adjustable-gain current output using a pMOS readout transistor in the linear region of operation. This paper discusses the pixel’s design and operation, and presents an analysis of the pixel’s temporal noise and FPN. Results for zero and first-order pixel mismatch are presented. The pixel was implemented in a both a 3.3 V 0.35 µm and a 1.8 V 0.18 µm CMOS process. The 0.35 µm process pixel had an uncorrected FPN of 1.4%/0.7% with/without column readout mismatch. The 0.18 µm process pixel had 0.4% FPN after delta-reset sampling (DRS). The pixel size in both processes was 10 X 10 µm2, with fill factors of 26% and 66%, respectively.
Biologically Inspired Vision Sensor for the Detection of Higher-Level Image Features
(2003-12-16) Van der Spiegel, Jan; Nishimura, Masatoshi
The paper briefly reviews certain aspects of the biological visual system and presents a smart vision sensor for the detection of higher-level features. The visual system processes information in a hierarchical manner starting from the retina up to the visual cortex. It decomposes the image in simple features (edges, orientation, line stops, corners, etc) using spatial and temporal information. At the higher level it integrates these primitive features, resulting in the recognition of complex objects. The sensor described in the paper is loosely modeled after the visual system and incorporates pixel level, programmable elements which extract orientation, end stops, corners and junctions from a line drawing. The architecture resembles a CNN-UM that can be programmed with a 30-bit word. The 16 x 16 pixels array detects these higher-level features in about 54 μseconds.
Multi-Frequency Pierce Oscillators Based On Piezoelectric AlN Contour-Mode MEMS Resonators
(2008-09-01) Zuo, Chengjie; Sinha, Nipun; Van der Spiegel, Jan; Piazza, Gianluca
This paper reports on the first demonstration of multi-frequency (176, 222, 307, and 482 MHz) oscillators based on piezoelectric AlN contour-mode MEMS resonators. All the oscillators show phase noise values between –88 and –68 dBc/Hz at 1 kHz offset and phase noise floors as low as –160 dBc/Hz at 1 MHz offset. The same Pierce circuit design is employed to sustain oscillations at the 4 different frequencies, while the oscillator core consumes at most 10 mW. The AlN resonators are currently wirebonded to the integrated circuit realized in the AMIS 0.5 μm 5 V CMOS process. This work constitutes a substantial step forward towards the demonstration of a single-chip multi-frequency reconfigurable timing solution that could be used in wireless communications and sensing applications.
Low-Power Reduced Transistor Image Sensor
(2009-07-16) Gruev, V.; Yang, Z.; Van der Spiegel, Jan
An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s.
Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter
(2001-09-02) Sargeant, Winslow; Laker, Kenneth R; Xu, Chao; Van der Spiegel, Jan
A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency.
A Spectral Conversion Approach to Single-Channel Speech Enhancement
(2007-05-01) Mouchtaris, Athanasios; Van der Spiegel, Jan; Mueller, Paul; Tsakalides, Panagiotis
In this paper, a novel method for single-channel speech enhancement is proposed, which is based on a spectral conversion feature denoising approach. Spectral conversion has been applied previously in the context of voice conversion, and has been shown to successfully transform spectral features with particular statistical properties into spectral features that best fit (with the constraint of a piecewise linear transformation) different target statistics. This spectral transformation is applied as an initialization step to two well-known single channel enhancement methods, namely the iterativeWiener filter (IWF) and a particular iterative implementation of the Kalman filter. In both cases, spectral conversion is shown here to provide a significant improvement as opposed to initializations using the spectral features directly from the noisy speech. In essence, the proposed approach allows for applying these two algorithms in a user-centric manner, when "clean" speech training data are available from a particular speaker. The extra step of spectral conversion is shown to offer significant advantages regarding output signal-to-noise ratio (SNR) improvement over the conventional initializations, which can reach 2 dB for the IWF and 6 dB for the Kalman filtering algorithm, for low input SNRs and for white and colored noise, respectively.
Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter
(2008-02-01) Farhat, Nabil H; Yuan, Jie; Van der Spiegel, Jan
A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6- µm CMOS pipeline analog-to-digital converter (ADC), which suffers from a high degree of nonlinear errors. The calibration gives improvements of 17 and 26 dB for signal-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, for the Nyquist input signal at the sampling rate of 33 MSample/s. The calibrated ADC achieves SNDR of 70.3 dB and SFDR of 81.3 dB at 33 MSample/s, which results in a resolution of about 12 b.
A CMOS Time to Digital Converter IC with 2 Level Analog CAM
(1994-09-01) Gerds, Eric J.; Van der Spiegel, Jan; Van Berg, Rick; Williams, Hugh H.; Callewaert, L.; Eyckmans, W.; Sansen, Willy
A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of < 35 ps, and a typical integral nonlinearity of < 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized.
A CMOS image processing sensor for the detection of image features
(2005-12-01) Nishimura, Masatoshi; Van der Spiegel, Jan
A compact CMOS vision sensor for the detection of higher level image features, such as corners, junctions (T-, X-, Y-type) and linestops, is presented. The on-chip detection of these features significantly reduces the data amount and hence facilitates the subsequent processing of pattern recognition. The sensor performs a series of template matching operations in an analog/digital mixed mode for various kinds of image filtering operations including thinning, orientation decomposition, error correction, set operations, and others. The analog operations are done in the current domain. A design procedure, based on the formulation of the transistor mismatch, is applied to fulfill both accuracy and speed requirements. The architecture resembles a CNN-UM that can be programmed by a 30-bit word. The results of an experimental 16x16 pixel chip demonstrate that the sensor is able to detect features at high speed due to the pixel-parallel operation. Over 270 individual processing operations are performed in about 54 µsec.
Two Transistor Current Mode Active Pixel Sensor
(2007-05-01) Gruev, Viktor; Van der Spiegel, Jan; Yang, Zheng; Etienne-Cummings, Ralph
A novel current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is 0.35% of the saturated current. A discussion on theoretical temporal noise limitations of this design is also presented.

Van der Spiegel, Jan

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