Van der Spiegel, Jan

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Electrical and Electronics

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Professor of Electrical Science and Engineering

Introduction

Research Interests Vision Sensors: We are studying novel current-mode image sensors with analog spatial processing and a new pixel array design, in which several techniques are combined to improve the quality of the images. Included in the design is a new addressing scheme that allows a group of pixels to share the same readout circuitry, therefore reducing the pixel size and increasing the resolution. The new design has removed the in-pixel accessing switches, and uses velocity saturated operation in order to increase the readout linearity. We are also integrating a successive approximation ADC on the imager. The ADC is natively current mode, and is designed to interface directly with the current mode pixels without the need for sample-and-hold circuits or current-to-voltage converters. Sensor for Polarization Imaging: We are also developing a focal plane imaging sensor capable of real time extraction of polarization information. The imaging system consists of a photo array of linear current mode active pixel sensors and analog processing circuitry for computation of the Stokes parameters. A dual-tier thin film micro-polarizer array has been deposited on the imager. A commercially available thin film polarizer is used to create an array of micro-polarizers. The thin film polarizer consists of an iodine-doped Polyvinyl Alcohol (PVA) layer which is patterned and etched using RIE. The measured extinction ratios of the filters are 1000 and 100 for the blue/green and red spectrum, respectively. Mixed mode Integrated Circuits for Data Acquisition Systems and Communications: We are currently exploring different architectures and algorithms to realize high performance analog-to-digital converters. One project deals background calibration schemes to correct for any residual non-idealities (linear and non-linear) in pipe-lined analog-to-digital converters. We are also developing CMOS circuits for RF communications using AlN Contour-Mode Piezoelectric Resonators in collaboration with Prof. G. Lucca’s group.

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1992 - 199972000 - 201040
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Now showing 1 - 10 of 47
  • Publication
    A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter
    (2003-07-01) Xu, Chao; Laker, Kenneth R; Sargeant, Winslow; Van der Spiegel, Jan
    A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.
  • Publication
    Fabrication of a Dual-Tier Thin Film Micro Polarization Array
    (2007-04-16) Gruev, Viktor; Ortu, Alessandro; Van der Spiegel, Jan; Lazarus, Nathan; Engheta, Nader
    A thin film polarization filter has been patterned and etched using reactive ion etching (RIE) in order to create 8 by 8 microns square periodic structures. The micropolarization filters retain the original extinction ratios of the unpatterned thin film. The measured extinction ratios on the micropolarization filters are ~1000 in the blue and green visible spectrum and ~100 in the red spectrum. Various gas combinations for RIE have been explored in order to determine the right concentration mix of CF4 and O2 that gives optimum etching rate, in terms of speed and under-etching. Theoretical explanation for the optimum etching rate has also been presented. In addition, anisotropic etching with 1μm under cutting of a 10μm thick film has been achieved. Experimental results for the patterned structures under polarized light are presented. The array of micropolarizers will be deposited on top of a custom made CMOS imaging sensor in order to compute the first three Stokes parameters in real time.
  • Publication
    Combined Software/Hardware Implementation of a Filterbank Front-End for Speech Recognition
    (2005-11-01) Mouchtaris, Athanasios; Cao, Yuan; Khan, Shehzad; Van der Spiegel, Jan; Mueller, Paul
    In this paper, a cost-effective implementation of a programmable filterbank front-end for speech recognition is presented. The objective has been to design a real-time bandpass filtering system with a filterbank of 16 filters, with analog audio input and analog output. The output consists of 16 analog signals, which are the envelopes of the filter outputs of the audio signal. These analog signals are then led to an analog neural computer, which performs the feature-based recognition task. One of the main objectives has been to allow the user to easily change the filter specifications without affecting the remaining system, thus a software implementation of the filterbank was preferred. In addition, the neural computer requires analog input. Therefore, we implemented the filterbank on a PC, with the input A/D and the output D/A performed by the PC stereo soundcard. Since multiple analog outputs are necessary for the neural computer (one for each filter), it then follows that the soundcard output should contain the multiplexed 16 filter outputs, while a hardware module is needed for demultiplexing the soundcard output into the final 16 analog signals.
  • Publication
    A Foveated Silicon Retina for Two-Dimensional Tracking
    (2000-06-01) Etienne-Cummings, Ralph; Van der Spiegel, Jan; Mueller, Paul; Zhang, Mao-zhu
    A silicon retina chip with a central foveal region for smooth-pursuit tracking and a peripheral region for saccadic target acquisition is presented. The foveal region contains a 9 x 9 dense array of large dynamic range photoreceptors and edge detectors. Two-dimensional direction of foveal motion is computed outside the imaging array. The peripheral region contains a sparse array of 19 x 17 similar, but larger, photoreceptors with in-pixel edge and temporal ON-set detection. The coordinates of moving or flashing targets are computed with two one-dimensional centroid localization circuits located on the outskirts of the peripheral region. The chip is operational for ambient intensities ranging over six orders of magnitude, targets contrast as low as 10%, foveal speed ranging from 1.5 to 10K pixels/s, and peripheral ON-set frequencies from <0.1 to 800 kHz. The chip is implemented in 2-μm N well CMOS process and consumes 15 mW (V dd = 4 V) in normal indoor light (25 μW/cm2). It has been used as a person tracker in a smart surveillance system and a road follower in an autonomous navigation system.
  • Publication
    A CMOS Linear Voltage/Current Dual-Mode Imager
    (2006-05-01) Gruev, Viktor; Yang, Zheng; Van der Spiegel, Jan
    We present a CMOS image sensor capable of both voltage- and current-mode operations. Each pixel on the image has a single transistor acting as either source follower for voltage readout, or transconductor for current readout. The two modes share the same readout lines, but have their own correlated double sampling (CDS) units for noise suppression. We also propose a novel current-mode readout technique using a velocity saturated short-channel transistor, which achieves high linearity. The 300x200 image array is a mixture of 3 types of pixels with identical photodiodes and access switches; while the readout transistors are sized for their designated mode of operation. This ensures a fair comparison on the performance of the different modes.
  • Publication
    Two Transistor Current Mode Active Pixel Sensor
    (2007-05-01) Gruev, Viktor; Van der Spiegel, Jan; Yang, Zheng; Etienne-Cummings, Ralph
    A novel current mode active pixel sensor for high resolution imaging is presented. The photo pixel is composed of a photodiode and two transistors: reset and transconductance amplifier transistor. The switch transistor is moved outside the pixel, allowing for lower pixel pitch and increased linearity of the output photocurrent. The increased linearity of the image sensor has greatly reduced spatial variations across the image after correlated double sampling and the column fix pattern noise is 0.35% of the saturated current. A discussion on theoretical temporal noise limitations of this design is also presented.
  • Publication
    An Extended Frequency Range CMOS Voltage-Controlled Oscillator
    (2002-09-15) Xu, Chao; Laker, Kenneth R; Sargeant, Winslow; Van der Spiegel, Jan
    This paper presents an extended frequency range CMOS monolithic voltage-controlled oscillator (VCO) design. A negative feedback control algorithm is used to automatically adjust the VCO range according to the control voltage. Based on this analog feedback control algorithm, the VCO achieves a wide range without any pre-register settings. Low phase noise is achieved by using both coarse control and fine control in VCO. A 600 MHz to 3.3 GHz monolithic CMOS PLL based on this wide range and low phase noise VCO has been fabricated in TSMC 0.18 μm, 1.8V CMOS technology and is used in many different applications such as FC, GE, and SONET etc.
  • Publication
    A 1.2 V, 38 microW Second-Order DeltaSigma Modulator with Signal Adaptive Control Architecture
    (2001-03-26) Van der Spiegel, Jan; Li, Qunying; Laker, Kenneth R
    A 1.2 V, 38 μW second-order ΔΣ modulator (ΔΣM) with a Signal Adaptive Control (SAC) architecture is fabricated in a 0.35 μm standard CMOS technology (Vt,n = 0.6V, Vt,p = -0.8V). This modulator achieves 75 dB dynamic range and 63 dB of peak SNDR at 6.8kHz Nyquist rate and an oversample ratio of 64. The proposed architecture effectively reduces the power dissipation while keeping the modulator performance almost unchanged.
  • Publication
    Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter
    (2008-02-01) Farhat, Nabil H; Yuan, Jie; Van der Spiegel, Jan
    A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6- µm CMOS pipeline analog-to-digital converter (ADC), which suffers from a high degree of nonlinear errors. The calibration gives improvements of 17 and 26 dB for signal-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, for the Nyquist input signal at the sampling rate of 33 MSample/s. The calibrated ADC achieves SNDR of 70.3 dB and SFDR of 81.3 dB at 33 MSample/s, which results in a resolution of about 12 b.
  • Publication
    A CMOS Time to Digital Converter IC with 2 Level Analog CAM
    (1994-09-01) Gerds, Eric J.; Van der Spiegel, Jan; Van Berg, Rick; Williams, Hugh H.; Callewaert, L.; Eyckmans, W.; Sansen, Willy
    A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of < 35 ps, and a typical integral nonlinearity of < 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized.

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